1. Field of the Invention
The present invention relates to memory devices, and more particularly, to a memory device that performs transmission and reception of data.
2. Description of the Related Art
In current computer systems and other devices, various buffers are used to perform data transmission and reception.
For example, a known device for transferring data inside a single central processing unit (CPU) is a stack memory, which is used as an area for temporarily saving data such as register data and the like due to interrupts and function calls. In general, the stack memory is implemented using a stack pointer on a standard one-dimensional memory.
A known device for transferring data between different CPUs is a shared memory having a software-based interface.
A known device for transferring data between a CPU and a memory is a cache memory.
Cache memories are data buffers with a relatively high degree of versatility since hardware control is performed, and there is no need for software that takes the hardware configuration into account. Also, because data swapping is automatically performed by hardware in cache memories, there is an advantage in that, regarding software-based data access, data swapping is seamless.
However, because cache memories are restricted to data transfer in units equal to the cache line size, they are inefficient at handling discrete data. In addition, because they were originally based on technology employing temporal and spatial locality of data access, they suffer from the problem that the cache capacity is wastefully used up when accessing data that is not reusable (that is, a part of the cache memories is meaninglessly occupied), and the performance is therefore reduced. They also suffer from the problem that the cache capacity significantly affects the computational performance of the CPU.
There is a known storage device provided with a stream buffer, combined with a cache memory, that can perform buffering without wastefully using up the capacity of the cache (that is, without occupying a part of the cache memory meaninglessly), even for data that is not reusable (for example, see Japanese Unexamined Patent Publication No. 09-319657).
However, stack memories and shared memories must be provided with dedicated hardware and software frameworks and therefore suffer from poor versatility. Moreover, the storage device described in Japanese Unexamined Patent Publication No. 09-319657 can be used only for transmitting and receiving data between a CPU and a memory, but it is difficult to use it in other configurations.
To summarize the above, hardware constituting conventional data transmitting-and-receiving devices must be appropriately modified to match the device(s) to be controlled (CPU and/or memory) for performing data transmission and reception. In other words, there is presently no suitable framework that can provide a unified infrastructure for any type of data communication.